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? semiconductor components industries, llc, 2000 june, 2000 rev. 3 1 publication order number: mc33351a/d

the mc33351a is a monolithic lithium battery protection circuit that is designed to enhance the useful operating life of three cell rechargeable battery packs. the mc33351a is specifically designed to be placed in a lithium battery pack where the battery cells continuously power it. in order to maintain cell operation within specified limits, the protection circuit senses cell voltages, and discharge current, and correspondingly controls the state of two pchannel mosfet switches. these switches are connected in series with the positive terminal of the third cell and the positive terminal of the battery pack. during a fault condition, the mc33351a open circuits the pack by turning off one of these mosfet switches. features ? selectable charge interrupt voltage sensing mode for precise cell voltage measurements ? programmable overvoltage delay ? choice of discharge current limit sensing elements consisting of either lowside resistor or highside mosfet switches ? programmable discharge current limit threshold and shutdown delay ? selectable cell voltage balancing ? virtually zero current sleepmode state when cells are discharged ? minimum external components for inclusion within the battery pack ? available in low profile surface mount package 5 lowside current limit input 4 discharge current limit shutdown delay typical three cell smart battery pack charge and discharge gate drive common 8 v cc / highside discharge current limit 16 mc33351a 2 discharge inhibit input cell 3 cell 2 cell 1/v c 15 ground 13 overvoltage shutdown delay 3 20 10 undervoltage fault output 1 charge inhibit input discharge gate drive output 7 charge gate drive output 9 6 11 highside discharge current limitthreshold charge interrupt mode select 17 18 balance 3 19 12 balance 2 14 balance 1 http://onsemi.com pin connections 20 1 120 17 16 15 14 13 3 4 5 6 7 8 (top view) charge inhibit input overvoltage shutdown delay charge interrupt mode select discharge gate drive output charge and discharge gate drive common balance 1 ground cell 1/v c balance 2 19 18 2 12 11 9 10 balance 3 v cc /high side discharge current limit cell 2 highside discharge current limit threshold discharge inhibit / test input discharge current limit shutdown delay lowside discharge current limit input charge gate drive output undervoltage fault output nc cell 3 tssop20 dtb suffix case 948e device package shipping ordering information mc33351adtb1 tssop20 75 units/rail mc33351adtb1r2 tssop20 2500 tape/reel marking diagrams mc35 1a1 alyw a = assembly location wl, l = wafer lot yy, y = year ww,w = work week
mc33351a http://onsemi.com 2 floating over/under cell voltage detector & reference oscillator balance 3 balance 2 balance 1 cell 3 cell 2 cell 1/v c ground over/under data latch & control logic cell selector cell voltage balancing logic r1 r2 r3 discharge current limit detector charge/discharge gate drivers sense enable 5 lowside discharge current limit input discharge current limit shutdown delay 1 charge inhibit input 2 discharge inhibit input r lim(ls) c dly 4 11 highside discharge current limit threshold 6 charge interrupt mode select overvoltage shutdown delay 3 v cc cell 1 control logic inputs from microcontroller output ports 10 k 10 k v c undervoltage fault output 10 cell 2 cell 3 13 20 15 14 12 19 18 17 16 v cc / highside discharge current limit mc33351a en ck ck charge and discharge gate drive common 8 charge gate drive output 9 discharge gate drive output 7 discharge switch q2 charge switch q1 10 k 10 k 10 k 4.7 m smart battery pack with lowside discharge current sensing, charge interrupt voltage sensing, and cell voltage balancing c i contro l logic out p ut to m icrocontro ll er i n p ut p ort figure 1. rg rg 5.1 k r t c t + 22 fd
mc33351a http://onsemi.com 3 floating over/under cell voltage detector & reference oscillator balance 3 balance 2 balance 1 cell 3 cell 2 cell 1/v c ground over/under data latch & control logic cell selector cell voltage balancing logic r1 r2 r3 discharge current limit detector charge/discharge gate drivers sense enable 5 lowside discharge current limit input discharge current limit shutdown delay 1 charge inhibit input 2 discharge inhibit input c dly 4 11 highside discharge current limit threshold 6 charge interrupt mode select overvoltage shutdown delay 3 v cc cell 1 control logic inputs from microcontroller output ports 10 k 10 k v c undervoltage fault output 10 cell 2 cell 3 13 20 15 14 12 19 18 17 16 v cc / highside discharge current limit mc33351a en ck ck charge and discharge gate drive common 8 charge gate drive output 9 discharge gate drive output 7 discharge switch q2 charge switch q1 10 k 10 k 10 k 4.7 m smart battery pack with highside discharge current sensing c i contro l logic out p ut to m icrocontro ll er i n p ut p ort r th(hs) rg rg figure 2. 5.1 k r t c t + 22 fd
mc33351a http://onsemi.com 4 maximum ratings ratings symbol value unit input voltage (measured with respect to ground, pin 13) v ir v cell 1/vc (pin 15) 7.5 cell 2 (pin 12) 10 cell 3 (pin 18) 18 vcc/ high side discharge current limit (pin 16) 20 charge inhibit input (pin 1) 7.5 discharge inhibit input (pin 2) 7.5 overvoltage shutdown delay (pin 3) 7.5 discharge current limit shutdown delay (pin 4) 20 lowside discharge current limit input (pin 5) 7.5 voltage sampling mode select (pin 6) 7.5 discharge gate drive output (pin 7) 18 charge gate drive common (pin 8) 20 charge gate drive output (pin 9) 18 undervoltage fault output (pin 10) 20 highside current limit threshold (pin 11) 7.5 cell balancing current (note 1) i bal ma balance 3, source current (pin 19) 50 balance 1, balance 2 sink current (pin 20, 14) 50 undervoltage fault output sink current (pin 10) i flt 10 ma thermal resistance, junctiontoair r q ja c/w dtb suffix, tssop plastic package, case 948e 135 dw suffix, so20l plastic package, case 751d 105 operating temperature (note 1) t j 40 to 150 c storage temperature t stg 55 to 150 c electrical characteristics (v cell 3 (pin 18) = 10.5v, v cell 2 (pin 12) = 7.0v, v cell 1 (pin 15) = 3.5v, c dly (pin 4) = 1000 pf, t a = 25 c) characteristic symbol min typ max unit voltage sensing cell charging cutoff (pin 15 to 13, 12 to 15, 18 to 12) overvoltage threshold, v cell increasing mc33351a1 v th(ov) 4.207 4.293 v overvoltage hysteresis, v cell decreasing v h 50 125 200 mv delay t dly(ov) one overvoltage sample (pin 3 = gnd) 0 1.2 s two consecutive overvoltage samples (pin 3 = vc) 1.0 2.3 s cell discharging cutoff mc33351a1 v th(uv) 2.185 2.3 2.415 v undervoltage threshold, v cell decreasing input bias current during cell voltage sampling i ib 28 m a cell voltage sampling rate t (smpl) 1.0 s charge interrupt v th(intrrpt) v input voltage range (pin 6) enabled (v c /2+0.2 to v c ) disabled (0 to v c /20.2) enabled charge interrupt time t intrrp 20 ms note: 1 maximum package power dissipation limits must be observed.
mc33351a http://onsemi.com 5 electrical characteristics (v cell 3 (pin 18) = 10.5v, v cell 2 (pin 12) = 7.0v, v cell 1 (pin 15) = 3.5v, c dly (pin 4) = 1000 pf, t a = 25 c) characteristic unit max typ min symbol cell voltage balancing internal balancing mosfet onresistance r ds(on) balance 3, (pin 19) 100 balance 1, balance 2 (pin 20, 14) 50 current sensing highside discharge current limit (pin 16 to pin 8) threshold voltage v th(hsdschg) r pin 11 = 1.0 m 200 280 380 mv r pin 11 = 2.0 m 100 170 230 mv delay overcurrent detect (v sense = 250 mv) t dly(hsdschg) 2.5 6.0 ms short circuit detect (v sense = 1.0 v) 0.0 2.5 ms lowside discharge current limit (pin 13 to pin 5) threshold voltage v th(lsdschg) 48 59 mv delay overcurrent detect (v sense = 50 mv) t dly(lsdschg) 2.5 6.0 ms short circuit detect (v sense = 200 mv) 0.3 0.4 ms logic charge and discharge inhibit inputs (pin 1, 2) threshold voltage v th(inhbt) v c /2 v propagation delay to respective gate drive output t pl/h 100 m s undervoltage fault output (pin 10) low state sink resistance 100 off state leakage current (v drain = 16v) 100 na detection delay time before discharge mosfet turn off (note 2) 16 s charge and discharge gate drive outputs (pin 9, 7) high state source resistance r ds(source) 100 low state sink resistance r ds(sink) 100 total device average cell current i cc operating (v cc = 12 v) 15 20 m a sleepmode (v cc = 6.0 v) 500 na minimum operating cell voltage v cc v cell 1 voltage 1.5 1.8 cell 2, or cell 3 voltage 0.7 0.8 note: 2 refer to avoltage sensingo text of operating description. guaranteed by design only; not tested .
mc33351a http://onsemi.com 6 figure 3. over voltage threshold versus temperature figure 4. charge on voltage threshold versus temperature figure 5. undervoltage threshold versus temperature figure 6. discharge current (low side) versus temperature 40 4 . 45 temperature ( c) 4.40 4.30 4.25 4.20 4.15 25 10 5 20 35 50 80 over voltage threshold (volts) 4.35 40 2.305 temperature ( c) 2.295 2.285 2.280 2.275 2.270 2.265 20 0 20406080 undervolta g e threshold (volts) 2.290 40 60 temperature ( c) 52 48 46 44 42 40 20 0 20406080 discharge current (low side) 50 65 40 4 .3 5 temperature ( c) 4.30 4.20 4.15 4.10 4.05 20 0 20 40 80 charge on threshold (volts) 4.25 60 2.300 threshold in millivolts 58 54 56 figure 7. discharge current (high side) threshold versus temperature (r11 = 1.5 mohms) figure 8. discharge current (high side) versus resistance 40 210 temperature ( c) 205 195 190 185 180 20 0 20406080 d i schar g e current (h ig h s i de) 200 0.7 350 resistance (m ) 270 230 210 190 170 150 0.9 1.1 1.3 1.5 2.1 discharge current threshold (mv) 250 1.7 1.9 330 290 310 threshold (millivolts)
mc33351a http://onsemi.com 7 figure 9. v cc versus i ee (no load) figure 10. v cc versus i ee (sleepmode) 9.5 4.0 v cc (v) (3 x v cell ) 3.8 3.6 3.4 3.2 3.0 10 10.5 11 11.5 12 i ee ( a) 7.0 v cc (v) = (3 x v cell ) 4.6 4.2 3.8 3.4 3.0 7.5 8.0 8.5 9.0 i ee (na) 5 . 0 4 . 2 m figure 11. discharge current limit shutdown delay versus capacitance 0 capacitance (pf) 200 150 100 50 0 5000 10000 15000 20000 time delay (i sense v 250 th to d gate ) (ms)
mc33351a http://onsemi.com 8 pin function description pin no. function description 1 charge inhibit input a logic low level at this input will disable battery pack charging. a 10 k internal pullup resistor connects from this pin to v c . 2 discharge inhibit input a logic low level at this input will disable battery pack discharging. a 10 k internal pullup resistor connects from this pin to v c . also, connecting this pin to 3.0v above v c the internal logic is held in reset state and both mosfet switches are turned on. 3 overvoltage shutdown delay this input controls the required number of cell overvoltage events that must be detected before charge switch q1 is turned off. with a logic level low at this input, charge switch q1 turns off after a single overvoltage event is detected. with a logic level high, charge switch q1 turns off after two successive overvoltage events are detected. 4 discharge current limit shutdown delay a capacitor connects from this pin to ground and is used to program a time delay from when the discharge current limit is exceeded to when discharge switch q2 is turned off. 5 lowside discharge current limit input this pin is used to monitor the load induced voltage drop that appears across current sensing resistor r lim(ls) . this voltage drop is sensed by pins 13 and 5. 6 charge interrupt mode select the logic level that is applied to this input determines if the charge current will be interrupted during the cell voltage sampling period. the charge current is interrupted when this input is connected to v c , and not interrupted when connected to ground, pin 13. 7 discharge gate drive output this output connects to the gate of discharge switch q2 allowing it to enable or disable battery pack discharging. 8 charge and discharge gate drive common this pin provides a gate turnoff path for charge switch q1. the charge switch source and the battery pack positive terminal connect to this point. 9 charge gate drive output this output connects to the gate of charge switch q1 allowing it to enable or disable battery pack charging. 10 undervoltage fault output this is an open drain output that is active low when an undervoltage fault limit has been exceeded. discharge switch q2 will turn off 16 seconds after the fault goes low. 11 highside discharge current limit threshold a resistor connects from this pin to ground and is used to program the highside discharge current limit threshold. the programmed threshold voltage is sensed by pins 16 and 8. 12 cell 2 this pin connects to a high impedance node of the cell selector where it is used to monitor the positive terminal of cell 2 and the negative terminal of cell 3. 13 ground this is the protection ic ground and all voltage ratings are with respect to this pin. 14 balance 2 this pin is used if cell balancing is desired. it connects to the drain of an internal nchannel mosfet and is active low during the balancing of cell 2. 15 cell 1/v c this is a multifunction pin that connects to a high impedance node of the cell selector where it is used to monitor the positive terminal of cell 1 and the negative terminal of cell 2. this pin also provides bias for the internal logic. 16 v cc /highside discharge current limit this is a multifunction pin that connects to a high impedance node of the cell selector where it is used to monitor the positive terminal of cell 3 and to provide positive supply voltage for the protection ic. this pin can also be used for highside discharge current limit protection by monitoring the load induced voltage drop that appears across the onresistance of switches q2 and diode of q1. this voltage drop is sensed by pins 16 and 8. 17 nc no connection 18 cell 3 this pin connects to a high impedance node of the cell selector where it is used to monitor the positive terminal of cell 3 and v cc . 19 balance 3 this pin is used if cell balancing is desired. it connects to the drain of an internal pchannel mosfet and is active high during the balancing of cell 3. 20 balance 1 this pin is used if cell balancing is desired. it connects to the drain of an internal nchannel mosfet and is active low during the balancing of cell 1.
mc33351a http://onsemi.com 9 protection circuit operating mode table outputs mosfet switches (note 3) cell balancing input conditions cell status circuit operation battery pack status charge q1 discharge q2 balancing outputs cell charging/discharging storage or nominal operation: no current or voltage faults both charge mosfet q1 and discharge mosfet q2 are on. the battery pack is available for charging or discharging. on on active cell charging fault/reset charge voltage limit fault: v cell v th(ov) for t dly(ov) t dly(ov) = 0 to 1.2 s, pin 3 to 13 1.0 to 2.1 s, pin 3 to 15 charge mosfet q1 is latched off and the cells are disconnected from the charging source. an internal hysteresis voltage is generated when the overvoltage cell is sensed. the shutdown delay is programmable for either one or two successive overvoltage events by the state of pin 3. the battery pack is available for discharging. on to off on active charge voltage limit reset: v cell < (v th(ov) v h ) for 1.2 s charge mosfet q1 will turn on when the voltage across the overvoltage cell falls sufficiently to overcome the internal hysteresis voltage. this can be accomplished by applying a load to the battery pack. off to on on active cell discharging fault/reset discharge current limit fault: v pin 16 (v pin 8 + vth (hs dschg) for t dly(hs dschg) or v pin 5 (v pin 13 + v th(ls dschg) f or t dly(ls dschg) discharge mosfet q2 is latched off and the cells are disconnected from the load. q2 will remain in the off state as long as v pin 16 exceeds v pin 8 by v th(hsdschrg) . a discharge current limit fault can be activated by either highside or a lowside current sensing methods. the battery pack is available for charging. on on to off active discharge current limit reset: v pin 16 v pin 8 < v th(hsdschrg) v pin 5 v pin 13 < v th(lsdschrg) the sense enable circuit will reset and turn on discharge mosfet q2 when v pin 16 no longer exceeds v pin 8 by 2.0 v. this can be accomplished by either disconnecting the load from the battery pack, or by connecting the battery pack to the charger. on off to on active discharge voltage limit fault: v cell v th(uv) for 2.1 s undervoltage fault output (pin 10) is driven low after two successive undervoltage events are detected. after a 16 second delay, discharge mosfet q2 is latched off, the cells are disconnected from the load, and the protection circuit enters a low current sleepmode state. the battery pack is available for charging. on on to off after 16 s disabled discharge voltage limit reset: v pin 8 > (v pin 16 + 0.6 v) the sense enable circuit will reset and turn on discharge mosfet q2 when v pin 8 exceeds v pin 16 by 0.6 v. this can be accomplished by connecting the battery pack to the charger. on off to on active faulty cell simultaneous charge and discharge voltage limit faults this condition can happen if there is a defective cell in the battery pack. the protection circuit will remain in the sleepmode state until the battery pack is connected to a charger. if cell 2, or 3 is faulty and a charger is connected, the protection circuit will cycle in and out of sleepmode. if cell 1 is faulty (<1.5 v) the protection circuit logic will not function and the battery pack cannot be charged. cycles cell 1 good disabled cell 1 faulty cycles cell 1 good disabled cell 1 faulty cycles cell 1 good disabled cell 1 faulty note: 3 charge switch q1 and discharge switch q2 can be selectively turned off via the appropriate inhibit input except during the sleepmode state.
mc33351a http://onsemi.com 10 operating description introduction the demand for smaller lightweight portable electronic equipment has dramatically increased the requirements of battery performance. today's most attractive chemistries include lithiumpolymer, lithiumion, and lithiummetal. each of these chemistries require electronic protection in order to constrain cell operation to within the manufacturers limits. rechargeable lithiumbased cells require precise charge and discharge termination limits for both voltage and current in order to maximize cell capacity, cycle life, and to protect the end user from a catastrophic event. the mc33351a features internallyfixed cell voltage limits, programmable cell voltage balancing, low operating current, a virtually zero current sleepmode state, and requires few external components. operating description the mc33351a is specifically designed to be placed in the battery pack where it can be continuously powered from three lithium cells. in order to maintain cell operation within specified limits, the protection circuit senses both cell voltage and discharge current, and correspondingly controls the state of two pchannel mosfet switches. these switches, q1 and q2, are placed within the series path of the positive terminal of cell 3 and the positive terminal of the battery pack. for lowside current limit sense, a resistor is placed within the series path of the negative terminal of cell 1 and the negative terminal of the battery pack. this configuration allows the protection circuit to interrupt the appropriate charge or discharge path fet in the event that a programmed voltage or current limit for any cell has been exceeded. a functional description of the protection circuit blocks follows. refer to the detailed block diagram shown in figure 1. voltage sensing individual cell voltage sensing is accomplished by the use of the cell selector in conjunction with the floating over/under voltage detector and reference block. the cell selector applies the voltage of each cell across an internal resistor divider string. the voltage at each of the tap points is sequentially polled and compared to an internal reference. if a limit has been exceeded, the result is stored in the over/under data latch and control logic block. the cell selector is gated on for a 4.0 ms period at a fixed one second repetition rate. this low duty cycle sampling technique reduces the average load current that the divider presents across each cell, thus extending the useful battery pack capacity. figure 12. simplified smart battery pack 4512 9 16 17 10 mc33351a cell 3 18 19 12 14 cell 2 cell 1 15 20 13 3 6 1 7 8 cell sensing sequence polling sequence time (ms) cell sensed tested limit 1 0.25 cell 1 overvoltage 2 0.25 cell 2 overvoltage 3 0.25 cell 3 overvoltage 4 0.25 cell 1 undervoltage 5 0.25 cell 2 undervoltage 6 0.25 cell 3 undervoltage by incorporating this polling technique with a single floating comparator and voltage divider, a significant reduction of circuitry and trim elements is achieved. this results in a smaller die size, lower cost, and reduced operating current.
mc33351a http://onsemi.com 11 figure 13. cell voltage limit sampling vs. programming from cell selector floating over/under cell voltage detector & reference discharge voltage threshold charge voltage threshold cell voltage return cell voltage + cell voltage r1 r2 r3 to cell selector the cell charge and discharge voltage limits are controlled by the values selected for the internal resistor divider string. as the battery pack reaches full charge, the cell voltage detector will sense an overvoltage fault condition on the first cell that exceeds the preset overvoltage limit. the fault information is stored in a data latch and charge mosfet q1 is turned off, disconnecting the battery pack from the charging source. an internal current source pullup is then applied to the lower tap of the divider when the overvoltage cell is again sensed. this creates an input hysteresis voltage with divider resistors r1 and r2. as a result of an overvoltage fault, the battery pack is available for discharging only. the overvoltage fault is reset by applying a load to the battery pack. as the voltage across the highest voltage cell falls below the hysteresis level, charge mosfet q1 will turn on and the current source pullup will turn off. the battery pack will now be available for charging or discharging. as the load eventually depletes the battery pack charge, the cell voltage detector will sense an undervoltage fault condition on the first cell that falls below the designed undervoltage limit. after an undervoltage cell is detected, undervoltage fault output goes low and discharge mosfet q2 is turned off, disconnecting the battery pack from the load after 16 seconds. the protection circuit will now enter a low current sleepmode state drawing less than 15.0 na typically, thus preventing any further cell discharging. as a result of the undervoltage fault, the battery pack is available for charging only. an alternate method of turning discharge mosfet q2 can be employed using r t and c t as shown in figures 1 and 2. recommended value of r t and c t of 5.1 k and 22 fd respectively generates a time delay of 110 10% milliseconds. the undervoltage fault is reset by applying charge current to the battery pack. when the voltage on pin 8 exceeds pin 16 by 0.6 v, discharge mosfet q2 will be turned on. the battery pack will now be available for charging or discharging. cell voltage balancing with series connected cells, successive charge and discharge cycles can result in a significant difference in cell voltage with a corresponding degradation of battery pack capacity. figure 13 illustrates the operation of an unbalanced three cell pack. as the cells become unbalanced, the full battery pack capacity is not realized. this is due to the requirement that charging must terminate when the highest voltage cell reaches the overvoltage limit, and discharging must terminate when the lowest voltage cell reaches the undervoltage limit. by employing a method of keeping the cell voltages equal, each of the cells can be charged and discharged to their specified limits, thus attaining the maximum possible capacity. figure 14. unbalanced battery pack operation disharge 4.0 v 4.2 v overvoltage limit charged 2.5 v undervoltage limit 2.7 v charge cell 3 cell 1 cell 2 discharged cell 3 cell 1 cell 2 the mc33351a contains a cell voltage balancing logic circuit that controls three internal mosfets. these mosfets are connected to an external transistor and resistor combination across the individual cells. the circuit samples the voltage of each cell during the polling period. if all of the cells are below the programmed overvoltage fault limit, no cell balancing takes place. if one or more cells reach the overvoltage fault limit, a specific latch is set for each cell. at the end of the polling period, charge mosfet q1 is turned off and the latches are interrogated. if all of the latches were set, no cell balancing takes place. if one, two, or three latches were set, the required cell balancing mosfets are then activated. the overvoltage cells are discharged to the preset level. as each cell attains this level, the balancing mosfets successively turn off. upon completion of cell balancing, charge mosfet q1 is turned on. cell voltage balancing can be active during charging and discharging, but is disabled during the low current sleepmode state. test mode a test option is provided to speed up device and battery pack testing. by connecting pin 2 to 3.0 v above v c the internal logic is held in a reset state and both mosfet switches are turned on. upon release, the control logic becomes active and the cell are polled within 4.0 ms.
mc33351a http://onsemi.com 12 discharge current sensing discharge current limit protection can be selectively added to the battery pack with the addition of a sense resistor r lim(dschg) on the lowside or by monitoring the voltage drop across the series fets on the highside. sense resistor lowside the sense resistor r lim(dschg) is placed in series with the negative terminal of cell 1 and the negative terminal of the battery pack, refer to figure 1. as the battery pack discharges, pins 5 and 13 sense the voltage drop across r lim(dschg) . a discharge current limit fault is detected if the voltage at pin 5 is greater than pin 13 by 50 mv for more than 3.0 ms. the fault information is stored in a data latch and discharge mosfet q2 is turned off, disconnecting the battery pack from the load. as a result of the discharge current fault, the battery pack is available for charging only. the discharge current limit is given by: i lim(dschg) v th(dschg) r lim(dschg) 50 mv r lim(dschg) voltage across fets highside a 1m w or 2m w resistor connected from pin# 11 to ground is used to program the highside discharge current limit threshold. the discharge current fault is reset by either disconnecting the load from the battery pack, or by connecting the battery pack to the charger. when the voltage on pin 16 no longer exceeds pin 8 by approximately 2.0 v, the sense enable circuit will turn on discharge mosfet q2. discharge current sensing can be disabled by connecting pin 16 to pin 8. the discharge current protection circuit contains a built in response delay of 3.0 ms. this helps to prevent fault activation when the battery pack is subjected to pulsed currents during charging or discharging. battery pack application each of the application figures show a capacitor labeled c i that connects directly across the battery pack terminals, and two resistors labeled r g that are placed in series with the charge and discharge gate drive outputs. these components prevent excessive currents from flowing into the mc33351a when the battery pack terminals are shorted or arced and are mandatory . capacitor c i is a 1.0 m f 20% ceramic leaded or surface mount type. it must be placed directly across the battery pack plus and minus terminals with extremely short lead lengths ( 1/16o) and as close to the ic as possible. the gate drive output resistors for both q1 and q2 are 10 k w 5.o% carbon film type. in applications where inordinately low leakage mosfets are used, the protection circuit may take several seconds to reset from an overcurrent fault after the load is removed. if desired, this situation can be remedied by providing a small leakage path for charging c i, thus allowing pin 8 to rapidly rise, so that it no longer exceeds pin 16 by approximately 2.0 v. a 4.7 m w resistor placed across the mosfet switches accomplishes this task with a minimum increase in cell discharge current when the battery pack is connected to the load. upon assembly of the battery pack, it is imperative that cell 1 be connected first so that v c is properly biased. the remaining cells can then be connected in any order. this assembly method prevents forward biasing the protection ic substrate which can result in overheating and nonfunctionality.
mc33351a http://onsemi.com 13 any cell voltage 4.25 v 2.30 v on off connected disconnected high (inactive) low (active) 16 sec (not resetable) charger discharge fet fault (pin 10) fault remains active no fault 1 sec + (0 1 sec) mc33351a cell voltage versus undervoltage fault
mc33351a http://onsemi.com 14 package dimensions tssop20 dtb suffix plastic package case 948e02 issue a dim a min max min max inches 6.60 0.260 millimeters b 4.30 4.50 0.169 0.177 c 1.20 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.27 0.37 0.011 0.015 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane w. 110 11 20 pin 1 ident a b t 0.100 (0.004) c d g h section nn k k1 jj1 n n m f w seating plane v u s u m 0.10 (0.004) v s t 20x ref k l l/2 2x s u 0.15 (0.006) t detail e 0.25 (0.010) detail e 6.40 0.252 s u 0.15 (0.006) t
mc33351a http://onsemi.com 15 notes
mc33351a http://onsemi.com 16 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent r ights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into t he body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402745 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc33351a/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (mf 1:00pm to 5:00pm munich time) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (mf 1:00pm to 5:00pm toulouse time) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (mf 12:00pm to 5:00pm uk time) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, england, ireland

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